The present invention relates to designing of semiconductor chips, and more particularly to an electro static discharge (ESD) protecting circuit adapted to provide an improvement a protection characteristic of a semiconductor chip.
Generally, semiconductor devices may be damaged due to an ESD phenomenon. Such a damage may occur at a wiring film or an oxide film. In either case, the damage may be considered as thermal damage.
The damage of oxide film means that a PN junction of a semiconductor device is partially melted due to an ESD phenomenon and thereby damaged. When the ESD phenomenon occurs, a current flows in the interface of the junction. This current flow results in an increase in temperature at the junction interface. As a result, a thermal runaway may occurs which causes a considerable decrease in resistance of the junction interface. Due to such a thermal runaway, the PN junction is partially melted and thereby damaged.
On the other hand, the damage of wiring film means that an aluminum wiring is fused due to a certain thermal factor and thereby opened by itself or bridged by the fused aluminum.
Such a damage of semiconductor device caused by the ESD phenomenon may be reduced using a primary method for removing the cause of ESD present around the devices. A secondary method may be also used which proposes the provision of an appropriate protection circuit for sequentially discharging ESD charging the device without affecting inner cells of the device.
The ESD protection circuit is constructed upon designing a semiconductor chip so as to protect inner cells from ESD generated at an external such as person or mechanical installation and a peripheral circuit. Typically, the ESD protection circuit is constituted by two pairs of diodes so as to discharge ESD charging a semiconductor device without affecting inner cells by utilizing forward and backward characteristics of the diodes.
Now, a conventional ESD protection circuit having the above-mentioned function will be described, in conjunction with FIGS. 1 to 3. FIG. 1 is a sectional view of the conventional ESD protection circuit. FIG. 2 is a circuit diagram of the ESD protection circuit shown in FIG. 1. FIG. 3 is a diagram illustrating an operation characteristic of the ESD protection circuit shown in FIG. 1.
As shown in FIG. 2, the ESD protection circuit includes four diodes D.sub.1 to D.sub.4. Referring to FIG. 1, the ESD protection circuit has a basic structure including an n type semiconductor substrate 1 and five p type wells 2 to 6. The first, second, third and fourth p type wells 2, 3, 5 and 6 are formed at a peripheral circuit region such that they are uniformly spaced from one another whereas the remaining p type well, namely the fifth p type well 4 is formed at a cell region where a circuit to be protected is formed.
For forming a diode structure having a PN junction in each p type well formed at the peripheral circuit region, a high concentration n type (n.sup.+) region and a high concentration p type (p.sup.+) region are formed in each p type well of the peripheral circuit region such that they are spaced a predetermined distance apart from each other.
In the p type well 4 formed at the cell region, a high concentration p type (p.sup.+) region is formed for reducing a contact resistance generated in the p type well 4. This p.sup.+ region of the p type well 4 is connected between a power supply source V.sub.DD and ground GND.
As shown in FIG. 2, the diode D.sub.1 is coupled at its anode electrode (the p.sup.+ type region in the first p type well 2 shown in FIG. 1) to a first pad and at its cathode electrode (the n.sup.+ type region in the first p type well 2 shown in FIG. 1) to the power supply source V.sub.DD. The diode D.sub.3 is coupled at its cathode electrode (the n.sup.+ type region in the second p type well 3 shown in FIG. 1) to the first pad and at its anode electrode (the p.sup.+ type region in the second p type well 3 shown in FIG. 1) to the ground GND. The diode D.sub.2 is coupled at its anode electrode (the p.sup.+ type region in the fourth p type well 6 shown in FIG. 1) to a second pad and at its cathode electrode (the n.sup.+ type region in the fourth p type well 6 shown in FIG. 1) to the power supply source V.sub.DD. The diode D.sub.4 is coupled at its cathode electrode (the n.sup.+ type region in the third p type well 5 shown in FIG. 1) to the second pad and at its anode electrode (the p.sup.+ type region in the third p type well 5 shown in FIG. 1) to the ground GND.
Operation of the conventional ESD protection circuit having the above-mentioned structure will now be described.
When the first pad is charged with ESD, the diodes D.sub.1 and D.sub.3 define a discharge path together and discharge the ESD through the defined discharge path without affecting the inner cell. On the other hand, when the second pad is charged with ESD, the inner cell can be protected by the diodes D.sub.2 and D.sub.4 which define an ESD discharge path together.
As shown in FIG. 3 illustrating the operation characteristic at each ESD discharge path, the conventional ESD protection circuit utilizes the forward characteristics of the diodes, namely, the diodes D.sub.1 and D.sub.2 and the backward characteristics of the diodes, namely, the diodes D.sub.3 and D.sub.4 simultaneously.
In the conventional ESD protection circuit, the discharge capability at each ESD discharge path is dependent on the area and concentration of the PN junction of each diode. For improving the performance of the ESD protection circuit, it is required to use an additional masking process upon designing the circuit. Furthermore, leakage current possibly generating at the PN junction affects directly the circuit performance when the device operates at a normal state.